1-Translate the following C++ program to MIPS assembly program (Please explain each instruction in your code by a comment and submit a .asm file).

2- Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.

a. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

42, 180, 46, 185, 189, 3, 181, 43, 6, 189, 65, 190

b. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with four-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

c. For each of these references, identify the binary address, the tag, and the index given a two way associative cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty

d. For each of these references, identify the binary address, the tag, and the index given a four way associative cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty

e. You are asked to optimize a cache design for the given references. There are four direct-mapped cache designs possible, all with a total of 32 words of data: C1 has 1-word blocks, C2 has 2-word blocks, C3 has 4-word blocks , and C4 has 8-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, C3 takes 5 cycles, and C4 takes 6 cycles, which is the best cache design?

There are many different design parameters that are important to a cache’s overall performance. Below are listed parameters for different direct-mapped cache designs.

Cache Data Size: 64 KiB

Cache Block Size:16 words

Cache Access Time: 2 cycle

f. Calculate the total number of bits required for the cache listed above, assuming a 32-bit address. Given that total size, find the total size of the closest direct-mapped cache with 4-word blocks of equal size or smaller. Explain why the first cache, despite its larger data size, might provide slower performance than the second cache.

3-Virtual memory use a page table to track the mapping of virtual address to physical addresses. The following data constitutes a stream of virtual addresses as seen on a system. Assume 4KiB pages, a 4-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, multiply the next largest page number by two.

12067,12060, 10740, 35522, 4222, 2428, 10744, 2444,4451

a. Given the address stream shown, the initial TLB and page table states provided above, show the final state of the system. Also list for each reference if it is a hit in the TLB, a hit in the page table, or a page fault.

b. Repeat a, but this time use 2 KiB pages instead of 4KiB pages. What would be some of the advantages of having a smaller page size? What are some of disadvantages?

4- Figure 4.2 of the text book shows the basic implementation of the MIPS subset, including the necessary multiplexors and control lines. With your own words, fully explain this figure.

5- Explain data hazard and structural hazard. Provide one example for each hazard.

6- Explain the role of compilers, assemblers, and linkers and how programs are translated into machine language and executed.