Project description:

Design a pipeline processor for the given single cycle CPU/datapath.

The ISA for this processor is given in the below:

The single cycle design of this process is shown below:

Your final project design section should include the following:

a. Overall description of each module you add.

b. Pipeline Diagram: One page per pipeline stage.

c. Pipeline registers: Provide a table that describes which values are being latched between stages. Adopt a signal naming convention, similar to the textbook by prefixing the signals with the stage name such as F, D, X, M, or W to distinguish in which stage the signal belongs.

d. Design Steps: Describe your approach for handling various control and datapath designs such as implementing the bypass logic, stalling logic, branch predictor, flushing, etc.

e. The project should be written as a formal report and should include the following sections:

i. Introduction

ii. Problem statement

iii. Design (sections: a, b, c and d)

iv. Name of each member who works on each section.

v. Conclusions

vi. References

vii. Appendix (should include any extra information related to the project)