The job of a digital design engineer is exciting. This project allows you to practice the FPGA design skills learnt in the lectures, laboratories and tutorials, as there is no better and more exciting way of understanding the material than applying it to solve a practical problem. The project has one task: Cube Root Finder.

1. Project specification

On 10/12/2007, Alexis Lemaire set a world record by finding the 13th integer root of a 200-digit number in only 70.2 seconds (http://en.wikipedia.org/wiki/Alexis_Lemaire). Inspired by this achievement, this project requires you to develop a high-speed FPGA design that calculates the cube root of an integer.

The FPGA device needs to satisfy the following specifications.

• It has two inputs ‘x’ and ‘start’: ‘x’ is an unsigned positive integer, and ‘start’ is a Boolean signal.

• The bit-width for ‘x’ is W bits, where W is a parameter specified in the PreLoadFcn function of the Simulink MDL file. W can be set to 8, 10, 20, 32, and so on.

• When input signal ‘start’ goes HIGH for one clock cycle, calculation should begin. It is assumed that signal ‘start’ will not go HIGH again until calculation is completed.

• The device has three outputs: ‘y’, ‘valid’, and ‘clock_count’.

• Output ‘y’ with a bit-width of W stores the cube root of ‘x’, calculated to the first binary digit. For example, for x = 18, output ‘y’ should be equal to 2.5d because

• When the device finishes calculating ‘y’, it should make output signal ‘valid’ go HIGH for exactly one clock cycle. It should also store in output ‘clock_count’ the actual number of clock cycles required to calculate ‘y’. For each example, if calculation starts at clock cycle 2 and finishes at clock cycle 102, then ‘clock_count’ = 102 − 2 = 100.

• The design must be created using MATLAB Simulink and Xilinx System Generator. The following built-in Xilinx blocks must not be used: MCode, Black Box, Natural Logarithm, Square Root.

For background information, see http://en.wikipedia.org/wiki/Cube_root.

On Moodle, there is a template file ‘Project_Task1_Template.mdl’ that contains the necessary input/output ports and start-up parameters. While you are free to move the existing blocks on the template file, do not modify their parameters. Rename the template file to the form of ‘Project_Task1_StudentID_Surname.mdl’ and start your work. For example, for student Jay Beta, ID 1123589, the design file should be ‘Project1_1123589_Beta.mdl’.

Create also a text file with name ‘Project_Task1_StudentID_Surname.txt’ that stores information about your design’s performance (clock counts and the numbers of Xilinx blocks). The file should have the following format where the blue text is relevant to your specific submission. Adhere to the strict formatting because during project marking, this file will be first processed by a computer program.