Material in the lecture is more general. Where there are apparent discrepancies use the lab specifications and requirements in this document. 

You must use System Verilog in this Lab. 

ALU 

The ALU should be coded using these integer operations *, +, -, and /. The integer operations built into are much more efficient than what you can do with the functions/modules you have learned. So, you do not have to build your own *, +, - and / functions in this lab, you can use these operators! 

Register File The register file must be implemented in a separate module. 

7-Segment display

The 7-segment display must be implemented using a function that converts digits to 7-segment display segments. 

ROM

A Read Only Memory should contain the program instructions for the program you will run. Your program will go in a ROM since the program is set and never changes during execution of the code. 

Debounce circuit

We will not use or include the debounce circuit in this lab, unless you experience a bounce problem during execution of your code. 

Microprocessor Control

This is implemented using a Finite State Machine. It should be split into a combinatorial always block and a synchronous always block, as usual. The combinatorial always block determines the next state of the controller. In each state the processor controller will do one of the steps necessary to execute the current opcode from the Instruction Register. 

The synchronous always block should store the current state (from the next state), the value of the program counter (from the next value), and the value of the W register (from alu_out). 

Code must be done in System Verilog, and always blocks should be always_comb, and always_ff. There should be no inferred latches. These are found during the Quartus synthesis and are errors in System Verilog. Points will be deducted for inferred latches. 

To avoid inferred latches, in your always_comb blocks, initialize all variables assigned in that block, and provide a default for every variable. 

As with all finite state machines, perform a reset first thing in the test bench and on the prototype validation using the programmed FPGA. 

Block Description

See the states of the controller in the figure below 

The Program Counter (PC) provides the address for the instruction to be executed. It should be incremented (PC=PC+1) in the “Register write back” cycle to point to the next instruction in the Instruction Memory (IM). But, if the current instruction is a JMP instruction, the PC will be updated during the "Register write back” cycle to point to the 'jump address provided to it by the Write Register. The initial value of PC must be 0, of course to begin at the first line of your program. 

The Instruction Memory is a 16-bit wide ROM with up to 256 locations. It outputs the instruction pointed to by the PC. You don't have to create a longer ROM than you need for the program. 

The Instruction Register (IR) contains the value Instruction Memory at address PC, and it should be available in that register by the end of the Fetch Cycle. 

The IR has four fields as indicated in Figure 1. OPCODE indicates which instruction is to be executed. RA points to a location in the Register File to be used as data A. RB points to a location in the register file to be used as data B. For the immediate operation LDI, for instance, the value of the Register file at address RD is loaded with {RA,RB). 

The Register File is a read/write memory which contains 16 8-bit values. Its ports RA, RB, and RD are decoded from the instruction register. RA and RB are addresses of data A and B, resp. which are used by the ALU, and RD is an address where the alu output Alu_out is written (after being stored in the W register) during the “Register write back” cycle. 

The ALU is the arithmetic logic unit which operates combinatorially on the values A from location RA in the register file, and B from location RB in the register file and generally puts the result back in the register file in location RD. The values of A and B must be available by the time the execute state (Execute Cycle) is performed. For immediate operations the ALU uses RA, and/or RB as values rather than as addresses. 

The W Register is a single 8-bit register that latches the results of the ALU operation during the Execute Cycle. 

The “Control” block will hold your state machine and whatever else you need to control the operation of this microprocessor. Some operations (for specific opcodes) are referred to as immediate because RA and RB are used directly instead of A and B. 

Description of state machine cycles 

•  The first cycle (IF or FETCH) uses the address specified in the Program Counter (PC) and loads the instruction at that location in the Instruction Memory into the Instruction Register (IR). Then decodes the IR (which has the 16-bit instruction into four four-bit fields: opcode, RA, RB, and RD (address registers) and fetches data from the Register File. 

•  The second cycle (FD or data fetch) fetch data A, B from the Register File using address RA, and RB 

•  The third cycle (EX or EXECUTE) executes the instruction using the ALU for the specific opcode and stores the result in the W register. 

•  The fourth (RWB or STORE) cycle writes the result of the EXECUTE cycle to the W-register and data memory-Register file (RF)In the case of a JMP instruction, to the PC. 

For timing reasons, I recommend that you assign (using a continuous assign statement) the instruction register to the ROM at location PC and assign OPCODE, RA, RB, RD using a continuous assign based on subset of bits in the IR (Instruction register). 

Looking at the block diagram of the MCU on the first page note that the registers (banks of flip-flops) are the blocks that have a clock input. These have a little > port on the block. Everything else should be combinatorial. Remember this. There will be homework problems to help with some of the blocks. 

Our microprocessor has it's own language (machine code), note: Boolean operations are bitwise 

Cout and OF should be 0 for all non-arithmetic operations

Overflow (OF) can be calculated using the most significant bits of the inputs, A[7] and B[7] for instance, and most significant bit of the output Alu_out[7] using the equation OF = (-A[7]^B[7]) &Alu_out[7];

Immediate commands refer to opcodes in which RA, RB, or RD are used as values rather than address in the register file where the value is located 

Step 2: Switches, LEDs, 7-segment Display and other board specifics should be as follows: 

1. SWO should be used as the asynchronous active-high reset signal. When on, you should be in reset (FSMs should start in their reset state and you should clear the contents of the register file on reset). 

2. CLOCK: The clock used for your state machine(s) should be the internal 50MHz clock (PIN_M9). Many students have timing issues using the 50MHz clock directly, so I recommend using a 50% frequency divider to divide down to perhaps 1000Hz (like the one given in Lab4). 

• Also see the next item regarding single-step mode. Single stepping is a way to step through the instructions in your code one at a time. Of course, in your test bench you will not use a 50MHz clock, use a convenient frequency in your test bench. Very high frequencies like 50MHz are not possible for your computer or Model Sim to process through multiple programming steps. 

3. SW1 will be used as a single-step mode switch. If SW1 is off (0) the microprocessor will execute whatever sequence exists in the ROM until it reaches a HALT instruction, using a the 50MHz built in clock. If SW1 is on (1), we will be in single-step mode. In this mode, the microprocessor will advance to the next state each time you let up on KEYO so that we can monitor various contents of the microprocessor as specified below. In this case KEYO is supplying the clock signal. 

4. KEYO will be used as the single-step advance button. This means that when in single-step mode (that is, SW1 is on (1)) every time we release KEYO we will advance to the next state. That is, in single stepping mode KEYO will be used as the clock. 

5. The 8 lowest LEDs (LED [7:0]) should normally indicate the address of the current instruction, which is the PC. That is, if we are executing the instruction at PC 8'b00011010, then the LEDs should display off-off-off-on-on-off-on-off. 

6. {SW4,SW3,SW2} will be used to select which output goes to the 7-segment display based on this table. Align the display to the right using the number of segments required for the desired display. 

there is some flexibility in the 7-segment displays you choose to assign to these display cases. 

Note: Obviously, it is not expected that we'll see the 7-segment display values and LEDs when in full-speed mode. It is, however, expected that these displays will be readable and display the correct data when in reset, halted at a halt instruction, or halted between instructions in single-step mode, or at the end of execution.

Left justify names, and right justify numbers. 

Requirements: 

1. Submission should include System Verilog code files along including the test-bench. Include the top-level module with this format. 

module lab5(input clk, reset, output logic [3:0] OPCODE, 

output logic [1:0] State,

output logic [7:0] PC, Alu_out, W_Reg, output logic Cout, OF ); 

This should be instantiated in your test bench. 

2. A log file in csv format written during the execution step, it should contain (use 

this order) 

PC, IR, OPCODE, RA, RB, RD, W_Reg, Cout, OF Use these headings on your columns. This log file is critical to show that your MCU works and will be compared against our expected result. It is important that you use this exact format. Write the numbers in this log file in hexadecimal format. Include your log file in your submission. 

Note: it is quite easy to do this in the test bench, but how to do that may not occur to you. You can write to a log file not only in the test bench but in any module. In any case write to the log file at the end of the execution cycle. If put it in a synthesizable module (that is not the test bench) comment the lines writing the log file for physical validation on the prototype board, because they will not compile and will be an error in Quartus. of the Lab5 module given above. 

3. Simulate the design first using a testbench. Submit the waveforms showing 

the PC, OPCODE, and W_Register for the first 5 values of PC, and then a separate screen grab of these values during the last 5 values of PC. 

4. Implement on your prototype board. Submit the Lab5.sof file. 

For programming your board, your top-level module should look like this. Include it in your submission. This module should contain an instance of the module in (1) above. This is a requirement of the lab. 

Note: Various problems can occur in this module. There are two key debugging steps. First, simulate the ... pv module in ModelSim to check for port errors/warnings. Any such errors/warnings will prevent you from successfully programming your board. Second, you may want to create a testbench for ..._pv module. It can be quickly built from the regular testbench and this can save you a lot of debugging time. 

module lab5_pv(input clk, SWO, SW1, KEYO, SW2, SW3, SW4, output logic [6:0] SevSeg5 SevSeg4, SevSeg3, SevSeg2, SevSegi, SevSego, 

output logic LEDO, LED1, LED2, LED3, LED4, LED5, LED6, LED7 ); 

programmed. 

6. Capture an image showing that the prototype board was 100% programmed. This should show the entire Quartus screen including the green progress bar. Also capture the Quartus Flow Summary in an image. 

7. For the physical validation capture an image of the 7-segment displays of the PC, OPCODE, and then the output of the ALU on the 7Segment display for PC address 8'h0A, and PC address 8'h12, and PC address 8'h13 and PC address 8’h14. This can be selected using switches in single stepping mode. 

8. Drop all these images in a PowerPoint presentation. Label the images for problem 3, including the PC for each. Label the answer to problem 5 as such, label answer to 6 as such. For problem 7 carefully to indicate the PC and address associated with of each image. This PowerPoint presentation should be saved as pdf. If the grader cannot figure which question your images go with or what they are images of, they will not be counted. 

Use this machine level program, this will be stored in your ROM