Objective:

Combinatorial Adder circuits using VHDL VHDL Adder dataflow implementation

Introduction:

A multiplexer performs the function of selecting one of several input lines Io, I1, I2 or I3 and presenting the selected input to the only output line Y. You can find multiplexer with 4, 8, or 16 inputs. These are referred to as 4 to 1, 8 to 1, or 16 to 1 multiplexers.

The general multiplexer circuit has 2n input signals, n select signals and 1 output signal.

One way is to use it to implement a hardware version of a truth table. The other way is to use it to convert parallel data bits into a stream of serial data bits.

Part 1. One Bit Wide 2 x 1 Multiplexer

The combinatorial logic circuit for the half adder is shown below.

The approach will be:

• Define the entity => Define the port => Define the architecture

For your design implement the following mapping

Input_A => switch_#02 -> LED_#02

• Input_B => switch_#01 -> LED_#01

• Input_SEL => switch_#00 => LED_#00

• Output_Y =>        => LED_#15

Make input_A = "1" using switch_#02

Make input_B = "0" using switch_#01

Using switch_#00

• Make Input_SEL => 0=>

• Make Input_SEL => 1=>

When you are done, program the board and complete the truth table above.

Is it what you would expect?