The bug trap's functionality and accuracy are to be further improved by the addition of a camera. To implement the required bug detection algorithms a number of new software routines are required. Your task is to implement these functions. Where required new instructions and additional hardware may be added to improve processing performance. However, to ensure compatibility with other systems the following restrictions are imposed: 

• The maximum clock speed used by the system is limited to 10MHz.

• Instruction names and machine code implementations i.e. bit fields used, are restricted to those defined in Appendix A.

• The assembler simpleCPUvid as.py may not be modified.

• Only a single macro file : simpleCPUvid.m4 may be used.

• The following ISE files may not be altered:

o CPU test-bench - cpu tb.vhd

o Computer schematic - computer.sch

o Processor schematic - simple_cpu_vld.sch

o Memory model – ram 4Kx16 sim vla.vhd

• Input images are limited to the file : bug24x24.ppm which can be downloaded from the Exam folder on the VLE.

• Output images are limited to 24x24 pixels in size and must use the PPM or PGM image formats, as defined in each question. 

The component symbols used in the schematic simple cpu vld may not be altered e.g. DATA MUX, COUNTER 12, ALU, REGISTER_FILE_4 etc. However, the hardware within these components can be modified e.g. you can not alter the ALU symbol, but you can add additional processing elements to the ALU schematic. 

You may implement any of the instructions defined in Appendix A. However, you do not need to do so to complete the programming tasks in questions 2,3 or 4. There are also two undefined instructions XOP1 (immediate) and XOP2 (register). You are free to modify the ALU and DECODER to implement new functionality for these undefined instructions. This functionality may be changed to suit the processing requirements of each question. The assembler simpleCPUvid_as.py has already been updated to support these new instructions and may not be altered.

Q1

To detect overflows during unsigned additions a new conditional jump instruction is required. This instruction should use the instruction format shown in figure 1. If the carry flag in the status register is set the processor should jump to the absolute address specified in the instruction, otherwise the program counter should be incremented to the address of the next instruction. 

Figure 1 : conditional jump instruction 

The file decoder.vhd has been updated to implement this new instruction and can be tested using the test code shown in Appendix B. The assembler simpleCPUvid_as.py has already been updated to support this new instruction. 

Write out the RTL descriptions of the micro-instructions used to perform this instruction during the Fetch, Decode and Execute phases, and briefly describe its operation. You should also identify what components / signals are used and the modifications made to the file decoder.vhd. These descriptions must be submitted as a plain text file named: jumpc.txt.

Appendix