Q4

Figure 6: pseudo code 

Generate PGM : Write a program to implement the pseudo code shown in figure 6. An initial solution to this problem is discussed on : 

http://simplecpudesign.com/simple_cpu_vld_image/index.html 

You are required to optimise this solution's processing performance and modify its implementation to meet the restrictions stated on page 2. 

This code converts RGB image data stored in memory into a grayscale image i.e. the function Y(). Each new pixel value is represented as an unsigned 8-bit value. Two pixels are packed into each memory location using "little-endian” format i.e. the first pixel is stored in the lower byte position. The grayscale image must be stored in memory at base address 1600. 

The brightness of each pixel should be calculated using the perceived brightness (Y) equation:

You may use different algorithms to calculate brightness, however, the brightness of each pixel must be within +/- 10% of the reference image output.pgm. This image can be downloaded from the VLE. The output image must use the PGM image format. Solutions not meeting these requirements will be awarded a zero mark. 

This program must be named: grayscale.asm and submitted as a plain text file. Again, the memory model ram_4Kx16_sim has already been configured to automatically load the tested image: bug24x24.ppm and store it at base address 1024. When your program has finished processing this image it must store the value 0x00 to address OxFFF to trigger the generation of the output image file: output.pgm. 

Note, as previously specified the grayscale image must be stored at base address  1600, with two pixel values stored in each memory location.

Your program must be capable of processing an image in 225 ms, programs not meeting this minimum requirement will be awarded a zero mark. Full marks will only be awarded if the program is capable of processing an image in less than 1.82 ms. 

The maximum execution time can be achieved using software only solutions. To achieve higher processing speeds new instructions and supporting hardware components will need to be added to the processor, as outlined in practical 9. 

Appendix